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5th
IEEE International Workshop on Silicon Debug and Diagnosis (SDD08)
Wednesday April 30th (4pm - 7pm) - Thursday May 1st (8am - 5pm), 2008
Scope & Mission
Troubleshooting how and why systems and circuits fail is important and is rapidly growing in industry significance. Debug and diagnosis may be needed for yield improvement, process monitoring, correcting the design function, failure mode learning for R&D, or just getting a working first prototype. This detective work can however become very tricky. Sources of difficulty include circuit and system complexity, packaging, limited physical access, shortened product creation cycle and time-to-market, the traditional focus on only pass/fail testing and missing tool and equipment capabilities. New and efficient solutions for debug and diagnosis will have a much needed and highly visible impact on productivity.
SDD08 will be held in San Diego, California, USA. It is the fifth in a series of highly successful technical workshops. Its mission and objective is to consider all issues related to debug and diagnosis of systems and circuits – from prototype bring-up to volume production.
The topics
of interest include, but are not limited to, the following:
- Debug Techniques
and Methodologies
- Design and Synthesis
for Debug
- DFT Reuse
for Debug and Diagnosis
- Debug & Diagnosis Architectures Tools
- Debug Standardization
- Microprocessor, FPGA, IP, SOC Debug
- Infrastructure IP for SDD
- Debug & Diagnosis Architectures
- Manufacturing & Prototype Environment
- Equipment Impact and Techniques
- Digital/Analog Turn-on
- Cross-geography turn-on, debug & diagnosis issues
- SDD vs. Yield & TTM
- Case Studies
For general information
contact:
Fidel Muradali
National Semiconductors
Email: fidel.muradali@nsc.com
For submission &
program information contact:
Bart Vermeulen
NXP Semiconductors
Email: bart.vermeulen@nxp.com
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The
5th IEEE International Workshop on Silicon Debug and Diagnosis (SDD07)
is sponsored by the Institute of Electrical and Electronics Engineers
(IEEE) Computer Society's Test Technology Technical Council (TTTC). |
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7th IEEE WORKSHOP on TEST of WIRELESS CIRCUITS and SYSTEMS (WTW 2008)
Sunday April 27th, 2008
The Wireless Test Workshop (WTW2008) is an IEEE-sponsored workshop devoted to exploring all issues relating to the design and especially test of wireless circuits and systems. The workshop will be held the day before the VLSI Test Symposium (VTS 2008).
WTW
Advance Technical Program
Rancho Bernardo Inn Golf Resort & Spa, San Diego, CA
Sunday,
April 27th, 2008
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8:30 am - 8:45
am |
Opening Address:
General Chair: R. Aitken - ARM
Program Chair: M. Slamani - IBM
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| 8:45 am - 10:00
am |
Session 1: Keynote Speaker & Invited Speaker |
| 8:45
am - 9:30 am |
The Convergence of Media and
Telecommunications Pushing Ahead
Christopher Douglass,
Wireless Strategy and Next
Gen Solution Executive
IBM Global Telecommunicatyions |
| 9:30 am - 10:00 am |
SiP/SoC Test Challenges
Octavio Martinez - Qualcomm
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| 10:00
am - 10:30 am BREAK - Student Poster Session |
| 10:30
am - 12:00 pm |
Session
2: Non-Traditional Test Techniques |
| 10:30
am - 11:00 am |
Towards 100Gbps: Scaling Trends for High-
Performance ATE
David Keezer - Georgia Tech |
| 11:00 am - 11:30 am |
Hybrid Non-Contact Testing for Advanced Packaging
Brian Moore - Scanimetrics Inc |
| 11:30 am - 12:00 pm |
Optimized Implementations of DC Testing for RF Products
Salem Abdennadher - Intel |
| 12:00 pm - 1:00 pm LUNCH |
| 1:00
pm - 2:30 pm |
Session
3: On-Chip/On-Board DFT |
| 1:00
pm - 1:30 pm |
Testing the DigRF 3G Baseband to RF Interface: BIST Allows a Low Cost Production Solution
Larry Luce - Freescale |
| 1:30 pm - 2:00 pm |
Automatic Matching Control System for Loadboard Test
Jaeseok Kim & William Eisenstadt - University of Florida;Ho-Hsin Yeh & Kathleen Melde - University of Arizona |
| 2:00 pm - 2:30 pm |
Range Calibration and Phase Noise Characterization of a High-Performance PLL with Integrated VCO
C. Montiel, C. Pearson, K. Vasanth, C. Yots, & P. Arora - Texas Instruments |
| 2:30 pm - 3:00 pm BREAK - Student Poster Sessions |
| 3:00
pm - 5:30 pm |
Session 4: Reliability & Built-in Test for Embedded Communications Circuits |
| 3:00
pm - 3:30 pm |
HTOL/Latch-up Issues on RF-CMOS Products: A Case Study
Gaurav Verma - Qualcomm
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| 3:30 pm - 4:00 pm |
Loop-Back Mode for Characterization of an Audio CODEC for Mobile Application
A. Owzar, E. Baykal, N. Haandbaek,W. Groeteweg, M. Helfenstein - NXP |
| 4:00
pm - 4:30 pm |
Robust RF BICS with Novel I-V Conversion Input Stage for 65-nm CMOS Technology
John Liobe & Martin Margala - University of Massachusetts Lowell |
| 4:30 pm - 5:00 pm |
Digitally-Assisted Analog/RF Testing for Wireless SoCs: A Weaver Image-Reject Receiver Case Study
Hsiu-Ming (Sherman) Chang & Kwang-Ting (Tim) Cheng Min-Sheng (Mitchell) Lin - University of California, Santa Barbara Broadcomm |
| 5:00 pm - 5:30 pm |
Student Poster Session |
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The 7th IEEE
Workshop on Test of Wireless Circuits and Systems (WTW 2008) is sponsored
by the Institute of Electrical and Electronics Engineers (IEEE) Computer
Society's Test Technology Technical Council (TTTC). |
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TTEP Tutorials at VTS 2008
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IEEE
TTTC Test Technology Educational Program
TTEP 2008
Tutorial 1 -- Tutorial 2 -- Tutorial 3
Tutorial 1: Sunday, April 27th 2008 - 8:30 am - 4:40 pm
Subject: Soft Errors: Technology Trends, System Effects, Protection Techniques and Case Studies
Presenters: Subhasish Mitra (Stanford University), Pia Sanda (IBM), Norbert Seifert (Intel)
Audience: Researchers and practitioners interested in architecture, modeling, design, CAD, test and reliability
Description: Radiation-induced soft errors are getting worse in digital systems manufactured in advanced technologies. Stringent data integrity and availability requirements of enterprise computing and networking applications demand special attention to soft errors in sequential elements and combinational logic. This tutorial discusses the impact of technology scaling on soft error rates, circuit-level modeling of soft errors, architectural impact of soft errors, challenges associated with evaluation of run-time behaviors of systems in the presence of soft errors, actual data on system behaviors in the presence of soft errors, metrics for quantifying soft error vulnerabilities, design of architectures with Built-in-Soft-Error-Resilience techniques, and actual case studies.
Tutorial 2: Thursday, May 1st, 2008 - 8:30 am - 4:30 pm
Subject: Practices in Analog, Mixed-signal and RF Testing
Presenters: Salem Abdennadher (Intel), Saghir Shaikh (Cadence)
Audience: This tutorial is most suitable for design, test and DFT engineers involved in actual implementation of mixed-signal, analog, RF and wireless devices and systems. The architects and engineering managers would also greatly benefit from this tutorial.
Description: The objective of this tutorial is to present existing industry ATE solutions and alternatives to testing of mixed-signal and RF SoCs. These techniques greatly rely upon DFT and BIST structures. The tutorial presents the basic concepts in analog and RF measurements (eye diagram, jitter, gain, power compression, harmonics, noise figure, phase noise, BER, etc.). Several industrial examples of production testing of mixed-signal and RF devices, such as, SERDES transceivers, PHYs, HSIO, and RF transceivers are also presented. The block-DFT solutions are presented for PLLs, CDR, equalizers, filters, mixers, AGC, LNAs, DACs and ADCs. The testing of high speed IO interfaces, such as, PCIe, and SATA, etc, and the new design trends in RF systems such as MIMO and SiP based systems and their testability are also presented in this tutorial.
Tutorial 3: Thursday, May 1st, 2008 - 8:30 am - 4:30 pm
Subject: Statistical Screening Methods Targeting "Zero Defect" IC Quality and Reliability
Presenter: Adit Singh (Auburn University)
Audience: Test and Reliability Engineers, Engineering Managers, Reliability and Quality Assurance Managers, Researchers and Research Students.
Description: Integrated circuits have traditionally all been tested identically in the manufacturing flow. However, as the detection of subtle manufacturing flaws becomes ever more challenging and expensive in aggressively scaled nanometer technologies, innovative new statistical screening methods are being developed that attempt to improve test effectiveness and optimize test costs by adaptively subjecting "suspect" parts to more extensive testing. The idea is similar to security screening at airports. Such methods fall into two broad categories: those that exploit the statistics of defect distribution on wafers, and those that exploit the correlation in the variation of process and performance parameters on wafers. This tutorial presents test methodologies that span both these categories, and illustrates their effectiveness with results from a number of recently published experimental studies on production circuits from several companies.
Additional registration and tutorials
information is available on http://www.tttc-vts.org |
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